The present invention relates to a method for integrated circuit substrate noise distribution and more particularly to noise distribution in noise sensitive differential or balanced integrated circuits.
The integration trend in design of digital radio for mobile telephony is to combine as many functions as possible into a single monolithic integrated circuit (IC). Digital portions and A/D and/or D/A converters are mainly designed by means of CMOS or BiCMOS processes. However, also analogue RF portions can be realized using the same technology as, for instance, described by S. Sheng et al. in a document titled xe2x80x9dA Low-Power CMOS Chipset for Spread-Spectrum Communicationsxe2x80x9d (International Solid-State Circuits Conference, 1996).
This demand for higher levels of integration is leading to the implementation of high-resolution analogue circuits within the same substrate as large digital systems produced by Very Large Scale Integration (VLSI). In such mixed-signal systems, the coupling of digital switching noise into sensitive analogue circuits can significantly limit the performance achieved in analogue signal processing and data conversion circuits. There is a significant dependence of the noise coupling through the substrate on the constitution of the silicon substrate. For instance this has been discussed by R. B. Merrill, W. M. Young, K. Brehmer in a paper titled xe2x80x9dEffect of Substrate Material on Crosstalk in Mixed Analog/Digital Integrated Circuitsxe2x80x9d (IEDM Tech. Dig. 1994, pp. 433-436).
The addition of AC grounded guard rings around the substrate noise generating and/or the noise sensitive circuits decrease the noise signal amplitude. The similar effect is achieved by the addition of pn-junctions to isolate the NMOS transistors from the substrate by e.g. adding an n-type buried layer under the p-well of NMOS transistor or an extra deep n-well surrounding the p-well, improves significantly the noise isolation by introducing junction capacitances between the transistors and the substrate as for instance demonstrated by U.S. Pat. No. 5,323,043. However, such techniques of pn isolation can""t be used for circuits containing bipolar transistors or for CMOS processes without these options. The use of guard rings is thus a main option to reduce the noise. Studying the noise sensitive differential circuits with grounded guard rings on different silicon substrates, i.e. low and high resistivity, it was realized that guard rings are inefficient for significant reduction of the noise amplitude on circuits made on low resistivity substrates. The reason is that the noise spreads efficiently in the substrates under the studied circuits. However, the difference in noise amplitude between the two differential inputs will be much lower than in the circuits using high resistivity substrates, even if in the last case the absolute value of the noise amplitude is much lower at each input terminal.
A method for noise distribution in noise sensitive differential or balanced Integrated Circuits is disclosed. Noise from an external noise source is made isotropic in relation to branches of a differential or balanced integrated circuitry by creating a low resistivity material path adjacent to at least two integrated transistors forming the differential or balanced integrated circuitry. The path of the low resistivity material is preferably made symmetrical in relation to the integrated transistors thereby forming a noise distributor for distributing the noise evenly. The noise distributor is formed as a floating substrate contact of the same doping kind as a substrate or a well within which the differential or balanced circuitry is contained. Furthermore the shape of the noise distributor will be optimized by simulations of the structure of the noise distributing low resistivity path, which structure does not need to be continuous as long as the low resistivity path is maintained.
A method according to the present invention is set forth by the independent claim 1 and further embodiments are set forth by the dependent claims 2 to 7.